To increase processor performance, clock frequencies used by microprocessors, often referred to as “CPUs”, have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as switching noise and signal integrity must be taken into account.
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often sent to help recover the data. The clock signal determines when the data should be sampled by a receiver's circuits. The clock signal may change state at the beginning of the time the data is valid. The receiver operates better when the clock signal is detected during the middle of the time the data is valid. Also, the clock signal may degrade as it travels from its transmission point. In both circumstances, a delay locked loop (DLL) can generate a copy of the clock signal at a fixed phase shift with respect to the original click signal.
FIG. 1 shows a block diagram of typical computer system components (5). Data (8) that is ‘N’ bits wide is transmitted from circuit A (6) to circuit B (7). To aid in the recovery of the transmitted data, a clock signal (9) is also transmitted with the data (8). The circuits (6,7) could also have a path (not shown) to transmit data from circuit B (7) to circuit A (6) along with an associated clock (not shown). The clock signal (9) may change from one state to another at the beginning of the data transmission to indicate when the data should be latched. A transition of the clock signal (9) temporally located some time after the beginning of when the data becomes valid is required for Circuit B (7) to properly latch the data. Furthermore, the clock signal (9) may have degraded during transmission. A DLL regenerates the clock signal (9) to a valid voltage and creates a phase shifted version of the clock signal to be used by other circuits, for example, a receiver's latching signal. The receiver's latching signal determines when the input to the receiver should be latched or sampled. The performance of a DLL is critical, and the DLL must maintain a proper reference of time with respect to a global clock signal on the CPU, or generically, an integrated circuit.
One common performance measure for a DLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, the clock signal (9) plus a known phase shift, should track the DLL output. For a signal with a repeated pattern, such as a clock signal, a transition that occurs from one state to another that does not occur at the same time relative to other transitions is said to have jitter. Jitter represents the perturbations that result in intermittent shortening or lengthening of signal elements. The DLL input, clock signal (9), may itself have jitter that may need to be transmitted to the DLL output. The DLL, however, may need to filter jitter created by other sources, such as power supply noise.
FIG. 2 shows a block diagram drawing of a representative DLL (200). Clock signal (201) is input to the DLL (200) to create a phased (i.e., delayed) output. Clock signal (201) is input to a voltage-controlled delay line (210) and to a phase detector (202). The phase detector (202) measures whether a phase difference between the clock signal (201) and an output, clk_out (217), of the delay path has the desired amount of delay. The phase detector (202) produces signals that control a charge pump (204). The phase detector (202) controls the charge pump (204) to increase or decrease its output current using signals up, U (203), and down, D (205). Internal biasing of the charge pump (204) maintains a nominal current output. The internal biasing of the charge pump (204) is dependent on bias signals VBP (209) and VBN (211). The signals up, U (203), and down, D (205), adjust the current output of the charge pump (204) with respect to the nominal current set by the control voltages, VBP (209) and VBN (211).
The charge pump (204) adds or removes charge from a capacitor C1 (206), that changes a DC value at the input of a bias-generator (208). The capacitor, C1 (206), is connected between a power supply, VDD, and a control signal , VCTRL (207). The bias-generator (208) produces control voltages (or bias voltages), VBP (209) and VBN (211), in response to the control signal, VCTRL (207), that control the delay of the voltage-controlled delay line (210) and maintain a nominal current output from the charge pump (204).
In FIG. 2, the voltage-controlled delay line (210) may be implemented using current starved elements. This means that the delays are controlled by modifying the amount of current available for charging and discharging capacitances. The linearity of a voltage controlled delay line's characteristics determines the stable range of frequencies over which the delayed lock loop can operate. An output of the voltage-controlled delay line (210), clk_out (217), represents a phase delayed copy of clock signal (201) which is used by other circuits.
Still referring to FIG. 2, the negative feedback created by clk_out (217) in the DLL (200) adjusts the delay through the voltage-controlled delay line (210) by integrating the phase error that results between the clock signal (201) and clk_out (217). The voltage-controlled delay line (210) will delay clk_out (217) by a fixed amount of time such that a desired delay between clock signal (201) and clk_out (217) exists. The speed of the DLL (200) response to a phase error is often related to loop bandwidth.
Delay locked loops are basically first order feedback control systems. As such, the delay locked loop can be described in the frequency domain as having a loop gain and a loop bandwidth. The loop bandwidth is the speed at which a signal completes the feedback loop of the delay locked loop to produce an update (i.e., error signal). Ideally, the DLL should have a high bandwidth so that the clock signal and data track each other. Noise, such as power supply noise will, however, have a certain noise-versus-frequency characteristic that may require the loop bandwidth to be reduced to attenuate the effects of the noise. The loop bandwidth determines to a large degree what portion of power supply noise is translated to jitter in the output of the DLL (200).